The present invention relates to a laminated memory in which a plurality of memories are laminated, and more particularly to a simultaneous operation control of the layers of laminated memory cores (hereinafter, referred to as memory core layers).
Recently, electronic equipment is reduced in size and semiconductor devices used in it are also reduced in size.
For example, a three-dimensionally laminated semiconductor device is used for small electronic equipment such as a mobile phone and the like. In the three-dimensionally laminated semiconductor device, a plurality of semiconductor chips are laminated and accommodated in one package in a state that they are connected to each other. A semiconductor device can be reduced in size by arranging it as a three-dimensionally laminated semiconductor device in which semiconductor chips are laminated as described above. MCP (Multi Chip Package), in which semiconductor chips are laminated, and PoP (Package on Package), in which small-sized packages are laminated in place of chips, have been developed as the three-dimensionally laminated semiconductor device so that the size of a semiconductor device is reduced and the operating speed thereof is increased.
The laminated semiconductor device includes a laminated memory in which memory chips are laminated, and the laminated memory includes a laminated DRAM in which, for example, a dynamic random access memory (hereinafter, referred to as DRAM) chips are laminated. The laminated DRAM can be arranged as a memory module or a semiconductor memory device having a large capacity by laminating a plurality of semiconductor chips. In a refresh operation and a parallel test of the laminated DRAM, all the layers of the laminated semiconductor chips are operated simultaneously. The simultaneous operation of all the memory core layers is an operation control mode suitable for simultaneous processing of a large amount of data in the refresh operation and the parallel test.
However, the laminated structure has an environmental condition specific to it in, for example, that power supply systems of the respective layers are dependently connected and that a temperature is different depending on the positions of the memory core layers. When all the memory core layers are operated simultaneously, a problem arises in that a power supply is varied by that transient currents are overlapped and that input/output characteristics are made unstable by the overlapped transient currents. To cope with the above problem, it is contemplated to use a method of sequentially operating memory blocks (banks) to be operated in parallel. However, some problems arise when a conventional sequential operation control method is used as it is.
WO2003/073430 (patent document 1) and Japanese Unexamined Patent Application Publication No. 1-004997 (patent document 2) are patent documents that relate to the conventional sequential operation control method. In the patent documents 1 and 2, the period of operation times of respective memory blocks are delayed so that an operation current is dispersed. In the patent document 1, when a flash memory is initialized, a control signal of each bank is delayed for a predetermined period of time. An operation current is dispersed by setting a different time as a time at which each bank is operated to thereby suppress a peak current. In the patent document 2, a control signal to each block is delayed for a predetermined period of time in a refresh operation of DRAM. The operation current is dispersed by setting a different period of operation time to each block to thereby suppress a peak current.
The simultaneous operation of all the layers of the laminated memory will be explained referring to FIGS. 1A-1C. FIG. 1A shows a side elevational view of the laminated memory, FIG. 1B shows a current waveform in the simultaneous operation, and FIG. 1C shows a current waveform in a sequential operation.
The laminated memory includes eight memory core layers 1 (1-#1 to 1-#8) laminated on a control logic layer 2. FIG. 1B shows the current waveform when all the eight memory core layers 1 are operated simultaneously. The current values of the respective layers are overlapped by simultaneously operating them. This results in a peak current value which is several times to eight times at maximum larger than the operation current. In this case, a power supply is varied because a transient current is overlapped and output characteristics are made unstable due to the variation of the power supply. Accordingly, when the conventional sequential operation control method is applied to the laminated memory, the current waveform is made as shown in FIG. 1C. Thus, the peak current value can be reduced.
As described above, in the conventional sequential operation, the control signal is delayed for a predetermined period of time (T) so that a sequential delay operation is carried out at a different period of operation time. As shown in FIG. 1C, when eight memory core layers are used, a current is dispersed to a total period of 7T+a by being delayed for the predetermined period of time (T). However, the sequential delay operation of the memory core layers is carried out in synchronism with an external clock at time intervals less correlating with an internal period of operation time. Accordingly, a problem arises in that a delay effect and a current dispersion effect are poor in a high speed clock and an overall period of operation time is remarkably increased in a low speed clock.
Further, when the sequential operation is started by a period of delay time in an external control circuit, the period of delay time in the external control circuit is different from the delay periods of time of operation of the respective layers. Accordingly, when the period of delay time in the external control circuit is short, the currents of the respective layers are overlapped. As a consequence, the current dispersion effect becomes poor. Thus, when the sequential delay operation is carried out by the external clock and the period of delay time in the external control circuit, it is difficult to set a proper period of delay time. In particular, in the laminated memory, the memory cores to be laminated have a different operation speed due to variation in manufacture. Further, the plurality of memory cores are dependently connected. Consequently, the power supply voltage supplied to the external control circuit and the peripheral temperature thereof are different from the power supply voltage supplied to the layered memory cores and the peripheral temperature thereof. Accordingly, since the period of delay time in the external control circuit is different from the delay periods of time of operation of the respective layers, a proper period of delay time is more difficult to be set.